SOI technology, especially using thin silicon top layers, which can be partially depleted (PD) or fully depleted (FD) already at very low bias voltages, are believed to become a key contributor to the continuous increase of circuit performance as predicted by Moore's law. Various press announcements show that the main IC manufacturers today are evaluating SOI for process generations capable of producing features of sizes less than 100 nm. Some of these manufacturers focus their production on PD SOI using industrially available SOI wafers, and all of them are evaluating the potential of FD SOI for low-power digital, mixed and RF applications. SOI technology today is mainly applied in the field of high-speed processor technology. Processors are now produced based on 90 nm CMOS PD SOI with speeds of about 1 to 1.6 GHz corresponding to a speed gain of about 20-25%.
It is well known to modify CMOS devices for PD or FD SOI. However, to adopt an RF BiCMOS process for PD or FD SOI is a much more complex task. There is no simple way of building bipolar devices on the thin SOI material with similar performance as on bulk material. However, U.S. Pat. No. 5,087,580 to Eklund, and J. Cai et al., Vertical SiGe-Base Bipolar Transistors on CMOS-Compatible SOI Substrate, p. 215 in Proceedings of the 2003 Bipolar/BiCMOS Circuits and Technology Meeting describe bipolar vertical-lateral transistors adopted for SOI.
As any RF process, i.e. CMOS, bipolar or BiCMOS process, includes a number of high-performance passive devices such as capacitors, resistors, varactors, inductors, etc., these devices have also to be redesigned for the new substrate material.
In previous processes on bulk silicon, a capacitor having high capacitance per area and high breakdown voltage is formed using a thin layer of silicon nitride deposited on top of highly doped silicon. A highly doped polycrystalline silicon layer region on top of the nitride serves as the top electrode. The bottom electrode consists of a subcollector layer and a collector plug arrangement to the upper side of the substrate. The thickness of the nitride layer is chosen so that the capacitor will obtain high capacitance values per area unit such as e.g. 2-4 fF/μm2.
The fabrication of such capacitors on bulk silicon is disclosed in U.S. Pat. No. 6,610,578 (inventors: H. Norström, S. Nygren and O. Tylstedt) and WO 02/091463 (inventors: T. Johansson, H. Norström and P. Algotsson).
A similar method to realize a capacitor is disclosed by H. Klose et al, B6HF: A 0.8 micron 25 GHz/25 ps bipolar technology for “Mobile radio” and “Ultra fast data link” IC-products, p. 25 in Proceedings of the 1993 Bipolar/BiCMOS Circuits and Technology Meeting. The capacitor is however described as ONO-type (ONO, oxide-nitride-oxide) with a capacitance value of 2 fF/μm2, which means that the fabrication method is different.
In other bulk processes for BiCMOS, substrate capacitors may consist of a MOS-similar structure, where the gate oxide serves as dielectric.
When using thin SOI layers, i.e. layers having a thickness of less than 200 nm, the isolation regions extend all the way down to the buried oxide layer, and thus the capacitor structures disclosed above cannot be fabricated.